This invention relates generally to digital frequency synthesizers and more particularly to indirect digital frequency synthesizers adapted to produce an output signal having a selected frequency within a band of frequencies with predetermined frequency separation.
As is known in the art, digital frequency synthesizers generally fall into two categories: direct frequency synthesizers and indirect frequency synthesizers. Direct synthesizers are typically open-loop configurations using frequency multipliers, frequency dividers, mixers and switches. While offering the advantage of fast frequency switching and generation of closely spaced frequencies, they are relatively hardware intensive and have a tendency of generating an excessive number of spurious signals. Indirect frequency synthesizers on the other hand are feedback loop configurations adapted to produce an output signal having a selected frequency within a spectrum of frequencies with a predetermined frequency separation. In one type of indirect synthesizer, the feedback loop translates a fixed offset frequency f.sub.os, which is near one end of the operating band, by an amount (f.sub.T) required to produce an output signal having the desired frequency, f.sub.d, i.e. f.sub.d =f.sub.os .+-.f.sub.T. More particularly, a reference frequency signal having a reference frequency f.sub.R is compared with a feedback signal, derived from the output signal, having a frequency related to the actual amount of frequency translation (f'.sub.T) provided to produce the output signal. As a result of this comparison, an error signal is produced which drives a voltage controlled oscillator (VCO) such that, in the steady state, the actual amount of frequency translation provided to the output signal (f'.sub.T) is equal to the required amount of frequency translation (f.sub.T) to produce the desired output frequency, f.sub.d. To provide rapid, accurate response a phase-lock loop is used for the feedback loop. In such phase-lock loop the feedback signal is fed to a programmable frequency divider prior to being compared with the frequency of the reference frequency signal. The division ratio N of the frequency divider is selected in response to a signal representative of the desired frequency, so that N is the ratio of the required translation frequency f.sub.T to the reference frequency f.sub.R i.e. N=f.sub.T /f.sub.R. Thus, in the steady state, the error signal produced by a phase detector drives the VCO so that in the steady state f.sub.d =f.sub.os .+-.Nf.sub.R depending on whether the offset frequency is near the lower, or upper, end of the frequency band, respectively. More particularly, the offset frequency signal is mixed with the output signal of the phase-lock loop to produce, in the steady state, the feedback signal having the translation frequency f.sub.T. The frequency of the feedback signal is divided by the integer N, selected in response to the frequency select input signal, such that N=f.sub.T /f.sub.R. Therefore, if the desired output frequency is f.sub.d, and assuming the offset frequency f.sub.os is below the lower end of the spectrum, N=(f.sub.d -f.sub.os)/f.sub.R. It follows that since N is an integer the minimum frequency separation attainable with such synthesizer is f.sub.R, the frequency of the reference frequency signal. An advantage of the indirect frequency synthesizer of this type s that spurious signal levels are reduced because of the low pass filtering action of the feedback loop. A disadvantage, however, is its longer frequency switching time compared with the switching time of a direct frequency synthesizer.
While such an indirect digital frequency synthesizer may be adequate in some applications it requires that the highest operating frequency of the programmable frequency divider generally be equal to, or greater than, the highest translation frequency f.sub.T. However, because commercially available digital frequency dividers have a fixed highest operating frequency, such synthesizer may, therefore, be limited in its application. One type of indirect digital synthesizer which reduces the required highest operating frequency of the divider by placing the offset frequency near the middle of the desired frequency range f.sub.d is described in copending application Ser. No. 07/272,044, inventors Zvi Galani, Malcolm E. Skinner, and John A. Chiesa, filed Nov. 16, 1988, and assigned to the same assignee as the present invention.
In still another type of indirect digital frequency synthesizer, a second phase-lock loop is provided for use in applications requiring closely spaced frequencies without high frequency division ratios. More specifically, a second phase-lock loop is used to synthesize a second offset frequency f.sub.os2 used by the first, or main phase lock loop. Such arrangement is shown in FIG. 1, where an indirect digital frequency synthesizer 10 is shown here to produce an output signal having a frequency within a band of 400 frequencies with a 1 MHz frequency separation. Thus, here synthesizer 10 is shown to include a first phase-lock loop 12. The first phase lock loop 12 (PLL1) is fed by a first reference frequency signal having a frequency f.sub.R1, here 10 MHZ, provided by a crystal oscillator 14 and the second offset frequency signal on line 16 having a frequency f.sub.os2 synthesized in a manner to be described hereinafter by a second phase-lock loop 18. The first phase-lock loop 12 includes a phase/frequency detector 20, the output of which, after being amplified by loop amplifier 22 and filtered by filter 24, drives a voltage controlled oscillator (VCO) 26. The phase/frequency detector 20 is here a model MC12040 sold by Motorola, Phoenix, Ariz. and includes appropriate filtering at its output to produce a signal representative of the phase between two signals fed thereto. When a first one of the fed signals leads a second one of the fed signals, a first one of a pair of outputs of the detector 20 produces a voltage proportional to the phase between the two fed signals while the second one of the pair of outputs is zero, whereas when the first one of the fed signals lags the second one of the fed signals the first one of the outputs is zero, and the second one of the pair of outputs produces a voltage proportional to the phase between the two fed signals. The VCO 26 produces an output signal at output port 28 having, in the steady state, the desired frequency f.sub.d. A portion of the output signal is fed, via a directional coupler 30, to a mixer 32. Also fed to mixer 32 is the second offset frequency signal synthesized by the second phase-lock loop 18. The resulting beat frequency, feedback signal is passed through low pass filter 34 to a programmable frequency divider 36. The output of divider 36 is fed to the phase/frequency detector 20, as shown. Likewise the second phase-lock loop 18 (PLL2) is fed by: a second reference frequency signal, having a frequency f.sub.R2, here a 1 MHZ, produced by passing the 10 MHZ reference input frequency signal produced by crystal oscillator 14 through a frequency divider 40, here a 10:1 frequency divider; and, a first offset frequency generator 42. The first offset frequency generator 42 produces a signal having an output frequency f.sub.os1 either above the upper, or below the lower end of the band of frequencies being synthesized (here below the lower end of the band). A portion of the signal synthesized by the second phase-lock loop 18 (for use as the second offset frequency of the first phase-lock loop 12) is coupled to a second mixer 44 via a directional coupler 46 along with the first offset frequency signal produced by generator 42. Thus the beat frequency feedback signal produced by the second mixer 44 and fed through low pass filter 48 is coupled to a second programmable frequency divider 50. The signal produced by the second programmable frequency divider 50 is fed to the phase/frequency detector 52 along with the 1 MHZ second reference frequency signal provided by the 10:1 frequency divider 40. The signal produced by the second phase/frequency detector 52 is fed to a second VCO 54 via loop amplifier 56 and filter 58. The signal produced by this second VCO 54 is fed to the first mixer 32, via line 16, and to the second mixer 44 via directional coupler 46. Completing the synthesizer 10 is a decoder 60, here including a conventional read only memory (ROM) which, in response to a digital word representative of the desired frequency f.sub.d to be synthesized, produces digital commands representative of the integer division ratios M and N for the first programmable frequency divider 36 and the second programmable frequency divider 50, respectively. It follows then that, in the steady state, the frequency of the second offset frequency signal produced by the second phase-lock loop 18 on line 16 will be f.sub.os2 =f.sub.os1 +Nf.sub.R2. Therefore, in the steady state, the frequency of the output signal at output port 28 will be f.sub.d =f.sub.os2 +Mf.sub.R1=f.sub.os1 +Nf.sub.R2 +Mf.sub.R1=f.sub.os1 +(N)MHZ+(10M)MHZ. The data stored in the decoder 60 to generate the desired frequency f.sub.d is presented in Table I below:
TABLE I __________________________________________________________________________ f.sub.d = (f.sub.T + f.sub.osl) = f.sub.osl + (10M + N)MHZ f.sub.d (MHZ) 0 1 2 3 4 5 6 7 8 9 M N M N M N M N M N M N M N M N M N M N __________________________________________________________________________ f.sub.osl +10 -- -- 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 f.sub.osl +20 1 10 2 " 2 " 2 " 2 " 2 " 2 " 2 " 2 " 2 " f.sub.osl +30 2 10 3 " 3 " 3 " 3 " 3 " 3 " 3 " 3 " 3 " f.sub.osl +40 3 " 4 " 4 " 4 " 4 " 4 " 4 " 4 " 4 " 4 " f.sub.osl +50 4 " 5 " 5 " 5 " 5 " 5 " 5 " 5 " 5 " 5 " f.sub.osl +60 5 " 6 " 6 " 6 " 6 " 6 " 6 " 6 " 6 " 6 " f.sub.osl +70 6 " 7 " 7 " 7 " 7 " 7 " 7 " 7 " 7 " 7 " f.sub.osl +80 7 " 8 " 8 " 8 " 8 " 8 " 8 " 8 " 8 " 8 " f.sub.osl +90 8 " 9 " 9 " 9 " 9 " 9 " 9 " 9 " 9 " 9 " f.sub.osl +100 9 " 10 " 10 " 10 " 10 " 10 " 10 " 10 " 10 " 10 " f.sub.osl +110 10 " 11 " 11 " 11 " 11 " 11 " 11 " 11 " 11 " 11 " f.sub.osl +120 11 " 12 " 12 " 12 " 12 " 12 " 12 " 12 " 12 " 12 " f.sub.osl +130 12 " 13 " 13 " 13 " 13 " 13 " 13 " 13 " 13 " 13 " f.sub.osl +140 13 " 14 " 14 " 14 " 14 " 14 " 14 " 14 " 14 " 14 " f.sub.osl +150 14 " 15 " 15 " 15 " 15 " 15 " 15 " 15 " 15 " 15 " f.sub.osl +160 15 " 16 " 16 " 16 " 16 " 16 " 16 " 16 " 16 " 16 " f.sub.osl +170 16 " 17 " 17 " 17 " 17 " 17 " 17 " 17 " 17 " 17 " f.sub.osl +180 17 " 18 " 18 " 18 " 18 " 18 " 18 " 18 " 18 " 18 " f.sub.osl +190 18 " 19 " 19 " 19 " 19 " 19 " 19 " 19 " 19 " 19 " f.sub.osl +200 19 " 20 " 20 " 20 " 20 " 20 " 20 " 20 " 20 " 20 " f.sub.osl +210 20 " 21 " 21 " 21 " 21 " 21 " 21 6 21 " 21 " 21 " f.sub.osl +220 21 " 22 " 22 " 22 " 22 " 22 " 22 " 22 " 22 " 22 " f.sub.osl +230 22 10 23 1 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23 9 f.sub.osl +240 23 " 24 " 24 " 24 " 24 " 24 " 24 " 24 " 24 " 24 " f.sub.osl +250 24 " 25 " 25 " 25 " 25 " 25 " 25 " 25 " 25 " 25 " f.sub.osl +260 25 " 26 " 26 " 26 " 26 " 26 " 26 " 26 " 26 " 26 " f.sub.osl +270 26 " 27 " 27 " 27 " 27 " 27 " 27 " 27 " 27 " 27 " f.sub.osl +280 27 " 28 " 28 " 28 " 28 " 28 " 28 " 28 " 28 " 28 " f.sub.osl +290 28 " 29 " 29 " 29 " 29 " 29 " 29 " 29 " 29 " 29 " f.sub.osl +300 29 " 30 " 30 " 30 " 30 " 30 " 30 " 30 " 30 " 30 " f.sub.osl +310 30 " 31 " 31 " 31 " 31 " 31 " 31 " 31 " 31 " 31 " f.sub.osl +320 31 " 32 " 32 " 32 " 32 " 32 " 32 " 32 " 32 " 32 " f.sub.osl +330 32 " 33 " 33 " 33 " 33 " 33 " 33 " 33 " 33 " 33 " f.sub.osl +340 33 " 34 " 34 " 34 " 34 " 34 " 34 " 34 " 34 " 34 " f.sub.osl +350 34 " 35 " 35 " 35 " 35 " 35 " 35 " 35 " 35 " 35 " f.sub.osl +360 35 " 36 " 36 " 36 " 36 " 36 " 36 " 36 " 36 " 36 " f.sub.osl +370 36 " 37 " 37 " 37 " 37 " 37 " 37 " 37 " 37 " 37 " f.sub.osl +380 37 " 38 " 38 " 38 " 38 " 38 " 38 " 38 " 38 " 38 " f.sub.osl +390 38 " 39 " 39 2 39 3 39 4 39 5 39 6 39 7 39 8 39 9 f.sub.osl +400 39 10 40 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- __________________________________________________________________________
Thus, for example, if the desired frequency, f.sub.d, to be synthesized is f.sub.os1 +235 MHZ from Table I, M=23 and N=5. From FIG. 1, it follows that the frequency of the signal fed to the second programmable frequency divider 50, in the steady state, will be 5 MHZ and the VCO 54 will produce a signal having a frequency f.sub.os2 =f.sub.os1 +Nf.sub.R2 =f.sub.os1 +5 MHZ. This signal is fed via line 16 to the first phase-lock loop 12 and hence the frequency of the signal fed to the first programmable frequency divider 36 will be, in the steady state, Mf.sub.R1 =230 MHZ with the result that the VCO 26 will produce an output signal having the desired frequency f.sub.os1 +235 MHZ. Thus the pair of phase-lock loops 12, 18 translate the first offset frequency f.sub.os1 an amount f.sub.T =Mf.sub.R1 +Nf.sub.R2 =235 MHZ. Here, the bandwidth of the translation frequency f.sub.T is 400MHZ. Further the frequency separation is thus equal to the frequency of the second reference frequency f.sub.R2, here the 1 MHZ signal fed to the second phase/frequency detector 52 of the second phase-lock loop 18. As is also known, the bandwidth of a phase-lock loop must be substantially smaller than the frequency of the reference frequency signal fed to such loop so that the loop provides adequate attenuation to the reference frequency signal leaking into the loop. Therefore, smaller frequency separation leads to narrower bandwidth phase-lock loops with the concommitant effect of increasing frequency switching time.